FPGA IP CORES
Intellectual Property Cores for Wide Range of Video Formats and Standards
Intellectual Property Cores for Wide Range of Video Formats and Standards
The HEVC HD Decoder Core by VYUsync is a highly optimized video decompression engine targeted primarily at FPGAs. The decoder achieves real-time performance for high definition (HD) video with ultra-low latency & optimized resource utilization. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does notrequire any external processor to aid the decode operation.The IO interface comprises of an input FIFO and an outputframe buffer. Decoded data can also be provided on a serialbus with embedded sync information. The decoder requiresDDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist orin source code format and can be customized to meet therequirements of end users.
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COMPLIANCE
HIGH PERFORMANCE
VIDEO FORMAT
INTERFACES
HIGHLY OPTIMIZED
HEVC HD decoder is fully compliant with the ISO/ IEC 23008-2 standard and ITU-T H.265 standard. The HEVC HD Decoder has been validated in hardware using conformance streams from ITU-T & other Industry standard test suites for functional and performance testing. It is a universal decoder.
This IP is filed, tested and proven in various customer applications. VYUsync’s HEVC HD decoder IP core is evaluated & purchased by leaders in Broadcasting Industry. The HEVC HD decoder supports all the features which are part of the H.265 standard with respect to the Profiles listed.
The HEVC HD Decoder is an Ultra-low latency decoder with robust error handling & resilience. It support Monochrome, Monochrome 12, Main, Main 10, Main 12, Main 4:2:2 10, and Main 4:2:2 12 profiles that allows for a bit depth of 8-bits to 12-bits per sample with support for 4:0:0, 4:2:0, and 4:2:2 Chroma sampling.
The HEVC HD Decoder is an Ultra-low latency decoder with robust error handling & resilience. It support Monochrome, Monochrome 12, Main, Main 10, Main 12, Main 4:2:2 10, and Main 4:2:2 12 profiles that allows for a bit depth of 8-bits to 12-bits per sample with support for 4:0:0, 4:2:0, and 4:2:2 Chroma sampling.
The HEVC HD Decoder is an Ultra-low latency decoder with robust error handling & resilience. It support Monochrome, Monochrome 12, Main, Main 10, Main 12, Main 4:2:2 10, and Main 4:2:2 12 profiles that allows for a bit depth of 8-bits to 12-bits per sample with support for 4:0:0, 4:2:0, and 4:2:2 Chroma sampling.
All the non-standard resolutions are supported by the decoder up to a maximum resolution of 1920 x 1080 and a maximum frame rate of 60. For example, monitor resolution 1600x900, 1,280×720 is supported..
The IO interface comprises of an input FIFO and an output frame buffer. The HEVC HD decoder accepts Elementary stream in Annex B Byte stream format. There is also an option for accepting Transport stream input when coupled with Transport Stream Demultiplexer IP.
The decoder requires DDR SDRAM to store reference pictures. The decoded pixels are written to DDR4 memory and decoded picture properties are signaled to the external system. The decoded data can also be provided in YUV data with embedded sync information.
The HEVC HD decoder can be implemented in the Xilinx Kintex Ultrascale and all 7-series FPGAs. The HEVC HD decoder on Intel Altera Arria 10 will be available on customer’s request. FPGA resources utilization for 1920 x 1080p60, 422, 10-bit, 75 mbps decoder is LUT’s -55,000, BRAM’s – 209 & DSP’s – 185. This does not include memory controller, display controller & TS demultiplexer.
The HEVC HD Decoder solution requires a total of 40-bit External memory running at 800 MHz. Typically 64-bit used instead of 40-bit. Memory bandwidth is calculated for the worst case inter prediction scenario where in all images are partitioned into 8x8 blocks which use bidirectional inter prediction..